Key Responsibilities
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Optimize CPU, cache, and interconnect performance
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Develop and enhance cycle-accurate performance simulators
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Perform microarchitecture analysis using simulation, emulation, and post-silicon data
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Build tools and methodologies for workload performance analysis
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Mentor junior engineers and collaborate with global cross-functional teams
Required Skills & Experience
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Strong computer architecture background (CPU, cache, interconnect)
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Proficiency in C++, scripting, and performance modeling
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Experience with RTL / Verilog HDL and hardware-software co-design
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Excellent analytical, problem-solving, and communication skills
Education
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BS / MS / PhD in EE, CS, CSE, or related field
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10+ years of hardware or microarchitecture design experience