Role Overview
As a CPU Verification Engineer, you will leverage your technical expertise to verify AMD’s next-generation CPU microprocessors. This role focuses on cache and Design-for-Test (DFT) verification, including MBIST, across block, core, and full-chip levels. You will work closely with architects, RTL designers, physical design, and silicon validation teams, contributing across the full product lifecycle—from specification through post-silicon validation.
Key Responsibilities
- Perform functional and DFT verification of high-speed microprocessor designs at RTL and gate levels across SoC, core, and block hierarchies.
- Develop and maintain verification environments, infrastructure, and automated regression frameworks.
- Create and execute detailed test plans using directed and constrained-random test methodologies.
- Verify cache subsystems and DFT features including MBIST, scan, JTAG (1149.x), and logic BIST.
- Develop and debug x86 assembly–based directed tests and random exercisers to validate functionality and testability.
- Analyze coverage metrics, identify verification gaps, and drive closure against quality targets.
- Resolve simulation discrepancies and assertion failures at behavioral and gate-level models.
- Support formal verification initiatives and contribute to methodology improvements.
- Collaborate with product test and silicon validation teams during bring-up and post-silicon debug.
- Replicate post-silicon issues using pre-silicon infrastructure to ensure full validation and characterization.
- Coordinate with cross-functional teams to manage dependencies and meet project milestones.
Required Skills & Experience
- Strong experience in functional and DFT verification of microprocessors or complex ASIC designs.
- Proficiency in Verilog HDL and logic simulation/debug.
- Hands-on programming experience with x86 assembly, C/C++, Perl, and/or Ruby.
- Solid understanding of modern CPU architecture and high-performance microprocessor design.
- In-depth knowledge of DFT methodologies including MBIST, scan (LSSD/MuxD), JTAG, and logic BIST.
- Familiarity with CMOS design fundamentals, deep sub-micron fault models, and fault simulation techniques.
- Exposure to formal verification tools and techniques is a strong plus.
Soft Skills & Attributes
- Strong written and verbal communication skills.
- Proven ability to collaborate across architecture, RTL, physical design, and validation teams.
- High level of ownership, initiative, and attention to detail.
- Ability to influence technical outcomes and manage priorities effectively in a fast-paced environment.
Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.