Role
We are looking for a highly analytical and detail-oriented engineer with strong problem-solving skills and a passion for innovation. This role involves working on long-term, complex programs, requiring self-motivation, accountability, and a consistent focus on meeting milestones. As we continuously push the boundaries of chip performance, candidates are expected to challenge conventional approaches and bring creative, forward-thinking solutions. Excellent written and verbal communication skills are essential, along with the ability to collaborate effectively within small teams and a large, cross-site Cores organization.
Key Responsibilities
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Serve as a technical lead for high-speed VLSI design using advanced deep submicron FinFET technologies
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Collaborate closely with RTL and physical design teams across multiple global sites to optimize power, performance, area, and delivery schedules
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Tackle complex design and EDA tool challenges by developing innovative, ground-breaking solutions
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Drive and champion technical innovation across projects and teams
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Prepare and deliver technical presentations for engineering peers and leadership
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Mentor and guide junior engineers, fostering technical excellence and growth
Preferred Experience & Qualifications
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Proven hands-on experience in high-speed VLSI design
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Strong understanding of computer architecture, digital hardware concepts, and design trade-offs
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Expertise in chip-level physical design and sign-off, including:
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Floorplanning, bus/pin planning
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Clock Tree Synthesis (CTS)
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Placement, optimization, routing
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Parasitic extraction and Static Timing Analysis (STA)
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IR drop, electromigration analysis
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Physical verification and final sign-off
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Ability to comprehend complex Verilog RTL and make minor modifications to improve timing or power
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Solid knowledge of digital circuit design, including high-speed flops, synchronizers, level shifters, and SRAM
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Familiarity with scripting and programming languages such as Perl, Tcl, and C