Role Overview
This role is responsible for planning, building, and executing verification and validation for new and existing features across AMD’s programmable devices. The primary technical focus is on PCIe/CXL, DMA, and related solution IPs. You will work closely with cross-functional teams to ensure robust, high-quality designs that meet performance and reliability goals.
The Ideal Candidate
You are passionate about modern, complex SoC architectures, with strong expertise in digital design, verification, and validation. You are a collaborative team player with excellent communication skills and experience working with globally distributed engineering teams. You bring strong analytical and problem-solving abilities, a willingness to learn, and the confidence to take ownership of challenging technical problems.
While deep expertise in at least one area of design, verification, or validation is expected, you should also have working knowledge across all stages of the development lifecycle.
Key Responsibilities
- Collaborate with architects, hardware, and firmware engineers to understand and verify new SoC features
- Architect and own moderate-complexity RTL designs (typically supported by one or two engineers) for integration into larger SoC platforms
- Develop comprehensive verification test plans, considering interactions with hardware, firmware, and software driver use cases
- Estimate development timelines for new tests and required enhancements to the verification environment
- Design and implement directed and constrained-random tests using class-based verification methodologies (preferably UVM)
- Debug issues across simulation, lab, and production systems, identify root causes, and collaborate with RTL and firmware teams to resolve defects
- Analyze functional and code coverage metrics and enhance tests or constraints to meet coverage goals
Preferred Experience & Skills
- Ownership of complex IP blocks; experience with high-speed I/O such as PCIe/CXL, DDR, Ethernet, or Video is highly desirable
- Strong debugging skills across RTL and firmware, using simulation and/or emulation tools
- Hands-on experience with UVM testbenches in Linux and Windows environments
- Proficiency in SystemVerilog and UVM-based verification frameworks
- Experience developing scalable verification processes, flows, and environments
- Workflow automation in distributed compute environments
- Exposure to simulation performance profiling and efficiency optimization
- Strong working knowledge of EDA tools, preferably in Linux environments
- Scripting experience with TCL, Python, Bash, or CSH
- Familiarity with FPGA and Adaptive SoC architectures and related development tools
Academic Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline