Job Summary
We are seeking an experienced High-Speed VLSI Design Engineer to lead and drive advanced chip design initiatives using deep submicron FinFET technologies. This role focuses on optimizing power, performance, and area (PPA) for next-generation CPU and core architectures. The ideal candidate brings strong analytical skills, innovation mindset, and the ability to collaborate across global, cross-functional teams.
Key Responsibilities
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Act as a technical lead for high-speed VLSI and physical design in advanced FinFET process nodes
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Collaborate with RTL, physical design, and architecture teams across multiple sites to achieve optimal PPA and on-time delivery
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Identify and solve complex design and EDA tool challenges, introducing innovative and scalable solutions
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Drive continuous improvement by challenging conventional design methodologies
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Create and present technical documentation and design reviews for peers and senior leadership
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Mentor junior engineers and support team development initiatives
Required Skills & Experience
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Hands-on experience in high-speed VLSI design and advanced node physical implementation
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Strong knowledge of computer architecture, digital hardware design, and performance trade-offs
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Expertise in chip-level physical design and sign-off, including:
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Floorplanning, bus and pin planning
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Clock Tree Synthesis (CTS)
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Placement, optimization, and routing
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Parasitic extraction and Static Timing Analysis (STA)
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IR drop and electromigration analysis
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Physical verification and tape-out sign-off
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Ability to analyze and modify Verilog RTL for timing and power optimization
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Solid understanding of digital circuits, high-speed flops, synchronizers, level shifters, and SRAM
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Proficiency in scripting and programming languages such as Perl, Tcl, and C
Desired Candidate Profile
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Strong analytical thinking and problem-solving abilities
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High attention to detail with a results-driven mindset
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Self-motivated and comfortable working on long-term, complex programs
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Excellent written and verbal communication skills
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Proven ability to work effectively in small teams and large, global engineering organizations
