Key Responsibilities
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Serve as a technical lead for high-speed VLSI physical design in deep sub-micron technologies
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Collaborate closely with RTL and physical design teams across multiple sites to optimize power, performance, area, and schedule (PPA)
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Drive innovative solutions to complex design and EDA tool challenges
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Prepare and deliver technical presentations to peers and senior leadership
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Mentor and guide junior engineers, promoting best practices and technical excellence
Preferred Experience & Skills
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Strong hands-on experience in high-speed VLSI physical design
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Solid understanding of computer architecture, hardware concepts, and design trade-offs
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Expertise in chip-level physical design flows, including:
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Floorplanning, bus and pin planning
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Clock Tree Synthesis (CTS)
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Placement, optimization, and routing
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Parasitic extraction and static timing analysis (STA)
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IR drop, electromigration analysis
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Physical verification and sign-off
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Ability to understand complex Verilog RTL and perform minor modifications for timing or power optimization
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Strong knowledge of digital circuit design, including high-speed flops, synchronizers, level shifters, and SRAM
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Experience with scripting and programming languages such as Perl, Tcl, and C
Qualifications
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BS or MS in Electrical Engineering, Computer Science, Computer Engineering, or related field