Role Overview
We are seeking a Physical Design Methodology Engineer to join AMD’s Central Physical Design Methodology Team. In this role, you will help define and optimize timing, power, and clocking methodologies for next-generation high-performance CPUs, GPUs, and machine intelligence silicon.
You will collaborate across multiple AMD teams, contributing to products ranging from low-power APUs to some of the world’s most powerful supercomputers.
Key Responsibilities
- Drive PVT corner analysis and frequency targets across multiple performance modes and guard bands
- Define and optimize physical implementation flows from synthesis through place & route for best performance per watt
- Collaborate with RTL and architecture teams to identify and resolve physical design bottlenecks
- Lead power budgeting, measurement, analysis, and tracking across designs
- Establish and standardize global physical design methodologies and best practices across libraries, flows, synthesis, and P&R
- Develop clock distribution methodologies, balancing skew, power, and jitter
- Create and maintain timing, clocking, power, and sign-off guidelines for advanced nodes
Preferred Qualifications & Experience
- Experience with advanced/sub-micron semiconductor process technologies
- Familiarity with CPU and/or GPU architectures
- Hands-on experience with power analysis tools such as PrimePower and/or PowerArtist
- Strong background in high-performance clocking and timing closure
- Expertise in STA methodologies, including OCV and advanced statistical margining techniques
- Proficiency in scripting languages (Perl, Tcl, Python)
- Strong data analysis and interpretation skills
Education
- MS or PhD in Electrical Engineering preferred
- Strong foundation in logic design, circuit design, and CAD tools for high-performance VLSI design