About Role:
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Functional & DFT verification at RTL and gate levels
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Cache, MBIST, scan, JTAG (1149.x) verification
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Development of verification environments, test plans & regression frameworks
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x86 assembly, C/C++, Perl/Ruby–based directed & random testing
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Coverage analysis, debug & post-silicon support
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Close collaboration with architects, RTL, physical design & silicon teams
Skills Required:
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Verilog HDL, simulation & debug
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Strong understanding of CPU architecture & DFT concepts
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Experience with microprocessor/ASIC verification
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Formal verification exposure is a plus
Education:
BS / MS / PhD in EE / CE